1. Field of the Invention
The invention relates to methods for fabricating micromachined structures, and more particularly, to methods for fabricating micromachined structures combining bulk substrate etching with micromachining.
2. Description of the Related Art
Microfabrication, also known as micromachining, commonly refers to the use of known semiconductor processing techniques to fabricate devices known as micro-electromechanical systems (MEMS) or micromachined devices. In general, known MEMS fabrication processes involve the sequential addition and removal of layers of material from a substrate layer through the use of film deposition and etching techniques until the desired structure has been realized. Accordingly, MEMS devices typically function under the same principles as their macroscale counterparts. MEMS devices, however, offer advantages in design, performance, and cost in comparison to their macroscale counterparts due to the decrease in scale of MEMS devices. In addition, due to batch fabrication techniques applicable to MEMS technology, significant reductions in per unit cost may be realized.
Micromachined structures are frequently used in MEMS inertial sensors, such as accelerometers and gyroscopes. A MEMS accelerometer using differential capacitors to detect acceleration typically includes three primary micromachined elements: a central, or proof mass, capacitor plates, and springs. FIG. 1 is a top plan view of a typical prior differential capacitor-based micromachined accelerometer 100, including a movable proof mass 102 supported by spring support beams 104. The proof mass 102 includes a plurality of electrodes 108 extending perpendicularly away from the proof mass 102, which are interleaved with a plurality of electrodes 110 extending perpendicularly from support beams 112. These features are formed in a cavity 116 formed in a substrate 118 through conventional etching techniques, and may be anchored to the underlying substrate 118 or cantilevered structures released from the substrate 118. The electrodes 108 and 110 are typically made of polysilicon or a material comprised of multi-films, such as silicon dioxide or aluminum, thereby creating individual parallel-plate capacitors between each adjacent pair of the interleaved electrodes 108, 110. In operation, when the accelerometer 100 is accelerated, the electrodes 108 move relative to the electrodes 110, thereby varying the distance, and hence the capacitance, between the electrodes 108, 110. The variable capacitance can be determined by peripheral circuitry interfacing with connectors 120, which are connected to the electrodes 110 via the support beams 112.
It is known, however, to use CMOS-micromachining processes to create microstructures that are mode out of the dielectric and metallization layers in a CMOS process. According to such processes, one of the CMOS interconnect metal layers, or some other layer made from an etch-resistant mask material, acts as an etch-resistant mask for defining the microstructural sidewalls. A reactive-ion etch of the CMOS oxide layer creates composite metal/dielectric microstructures that can have a high aspect ratio of beam width to beam thickness, and of gaps between the beams to beam thickness.
There are two primary techniques to refine and release CMOS micromachined structures: wet etching and dry plasma etching. Wet etching provides that disadvantage that it generally cannot reproduce complex shaped structures with accurate dimensional control. Dry plasma etching, on the other hand, typically is free from dimensional restrictions. However, the current semiconductor-based plasma systems used for dry plasma etching have very low etch rates, for example, below one μm/min for silicon. The disadvantage is particularly acute when the CMOS microstructure is to be combined with, for example, a bulk silicon substrate, which may have a thickness between 400-500 μm.
A known prior solution for fabricating submicron movable mechanical structures uses a chemically assisted ion beam etch (CAIBE) and a reactive ion etch (RIE). According to the process, an RIE is performed to selectively remove portions of dielectric layers formed on a substrate, such as a GaAs substrate. Next, a CAIBE is performed to selectively remove portions of the GaAs substrate to define the trenches of the structure. Subsequently, a mitride layer is deposited over the structure, including the trenches, by plasma-enhanced chemical vapor deposition (PECVD) to protect the mesa structure. After the nitride layer is formed, the portions of the nitride layer are etched back remove the nitride layer from the bottoms of the trenches, but to retain the nitride layer on the sidewalls of the mesa structure. Next, an RIE process can be used to undercut the substrate material under the structure. This solution thus requires the deposition of materials to protect the microstructure during the etching of the substrate layer, which therefore increases production steps and consequently production cost.
In order to solve above-mentioned problems, referring to FIGS. 2a to 2c, U.S. Pat. No. 6,458,615 discloses a method for fabricating micromachined structures. First, referring to FIG. 2a, a circuitry layer 12 is formed on a substrate 14. The substrate 14 is the lowest layer of material on a wafer. The circuitry layer 12 may be, for example, a CMOS circuitry layer, including CMOS circuitry regions and CMOS interconnect regions 16, formed on the substrate 14 according to conventional CMOS fabrication techniques. The circuitry layer 12 may include dielectric layers 20, polysilicon layers 17 and metal layers 18, including an upper metal layer 19. The dielectric layers 20 may be a silicon dioxide layer.
Next, portions of the dielectric layers 20 of the CMOS circuitry layer 12 are removed by a reactive ion etch (RIE) and the upper metal layer 19 acts as the etching mask. Subsequently, a deep reactive ion etch (DRIE) process is used to remove the portion of the substrate 14 exposed by the upper metal layer 19. The resulting structure assembly is illustrated in FIG. 2b. Next, the substrate assembly is subjected to an isotropic etch to remove the beam springs 28 so that the microstructure 22 is released from the substrate 14. The resulting structure assembly is illustrated in FIG. 2c. 
However, according to the above method for fabricating micromachined structures, the isotropic etch is required to be precisely timed to prevent the substrate material under the CMOS circuitry regions 15 and CMOS interconnect regions 16 from over-etching.
Accordingly, there exists a need to provide a method for fabricating micromachined structures to solve the above-mentioned problems.